Webinars

As the role of PCIe technology expands in new areas such as AI/ML, PCI-SIG has recognized the need to support multi-path fabrics with an ordering model to improve PCIe bandwidth and reduce latency while maintaining backwards compatibility. Unordered IO (UIO) is a new feature added to the PCIe 6.1 specification that defines a new wire semantic protocol and related capabilities for addressing the limitations of the existing PCIe fabric-enforced ordering rules, while keeping the producer-consumer ordering model intact. UIO is a key enabler for Multi-Link PCIe devices (i.e., non-tree topologies). UIO also helps improve the interaction with other protocols, including on-die/on-package protocols, such as CXL, UCIe, etc. Attendees of this webinar will understand the traditional PCIe ordering model, the system-level considerations and tradeoffs for deploying PCIe Unordered IO and will learn which applications and market segments will benefit most from deploying UIO.

Presenters:

Debendra Das Sharma (Intel)
Steve Glaser (NVIDIA)

The Journey to CopprLink™ and Beyond: An Exploration of PCIe® Cabling Solutions
July 11, 2024, 8:00 am PDT

As the need for PCIe cabling has grown, PCI-SIG has kept pace with the industry demand for high-speed cabling solutions in applications like disaggregated servers, data center networking, storage, AI, automotive and more. In May 2024, PCI-SIG released the CopprLink Internal and External Cable specifications for PCIe 5.0 and 6.0 technology, providing internal and external cabling solutions at 32.0 and 64.0 GT/s.

The release of CopprLink Internal and External Cable specifications is the latest step on a journey toward PCIe cabling solutions that meet evolving industry needs. By providing internal and external cables of varying speeds and reach that utilize existing connector form factors, PCI-SIG is ensuring the industry can choose the best PCIe cabling solution for their applications. Along with the CopprLink Internal and External Cable specifications, PCI-SIG is exploring an optical interconnect for data-demanding applications like AI, cloud computing and HPC.

In this webinar, attendees will learn:

An overview of current PCI-SIG cabling efforts – past, present and future
The application space for PCIe cabling, including data center networking, AI, storage and more
The future of PCIe cabling as PCI-SIG explores an optical interconnect and PCIe 7.0 technology at 128 GT/s

Participants:

Samuel Kocsis (Amphenol)
Mohiuddin Mazumder (Intel)

Celebrating 20 Years of the PCI Express® Specification
April 10, 2024, 9:00 am PST

Exploring the Technical Differences Between PCI Express Specification Revisions Webinar

Over the past 20 years and six generations, the PCI Express® (PCIe®) specification has been the industry’s high-speed I/O interconnect of choice for applications ranging from personal computers to advanced AI platforms. First introduced by PCI-SIG® in 2003, PCIe architecture uniquely meets the industry need for a system interconnect with greater bandwidth scalability and lower cost of implementation. The latest version, PCIe 6.2 specification provides 64 GT/s raw bit rate (up to 256 GB/s via a x16 configuration) for markets such as AI/ML, storage, networking, automotive, HPC and more.

In this webinar, a panel featuring PCI-SIG Board members and workgroup chairs will discuss the past, present and future of the PCIe specification, including the impacts of PCIe technology in the industry and the new and emerging markets that will benefit most from PCIe technology. Panelists will also cover the expansion of the PCI-SIG Compliance Program, the transition from NRZ to PAM4 signaling, and the future of PCIe technology as we prepare for the PCIe 7.0 specification in 2025.

Participants:

Moderator: Mihaela Erler (Intel)
Debendra Das Sharma (Intel)
David Harriman (Ampere)
Manisha Nilange (Intel)
Richard Solomon (Synopsys)

July 27, 2023

For more than two decades, PCI-SIG® has delivered industry-leading PCI Express® (PCIe®) specifications, remaining ahead of the demand for a high-bandwidth, low-latency interconnect for compute-intensive systems. Starting with the PCIe 1.0 specification in 2002, PCI-SIG has doubled the I/O bandwidth with each subsequent generation. Considering the entire catalogue of PCIe specifications, there are many different factors to consider when choosing the right PCIe generation for an application, including power, bandwidth, signal integrity, reach and data transfer rates.

In this webinar, a panel of industry experts from PCI-SIG member companies will discuss the technical differences between the PCIe specifications – from PCIe 3.0 specification (8 GT/s) to PCIe 7.0 specification (128 GT/s). The PCIe 4.0 and PCIe 5.0 specifications (16 GT/s and 32 GT/s) are the current industry standards, while PCIe 6.0 (64 GT/s) technology market adoption is now underway. The PCIe 7.0 specification is under development and on track for release in 2025, targeting data-demanding applications such as 800 G Ethernet, AI/ML, Cloud and Quantum Computing and Hyperscale Data Centers.

Participants will learn the technical considerations of PCIe technology, including:

Differences in electrical signal reach between the PCIe specifications
Maximum latency for each PCIe technology generation
Challenges of PCIe 5.0 specification adoption and the jump to PCIe 6.0 technology
Shift from NRZ to PAM4 signaling and the addition of Flit mode
The diverse applications of PCIe technology and implementation approaches

Participants

Moderator: Scott Knowlton (Synopsys)
Richard Ward (Astera Labs)
Timothy Pezarro (Microchip)
Matt Burns (Samtec)

PCIe® 5.0 Protocol and Electrical Compliance Testing Deep Dive

January 25, 2023

The History of PCI IO Technology: 30 Years of PCI-SIG® Innovation

PCI-SIG® Compliance Workshops are events where PCI-SIG members can participate in interoperability and compliance testing for the PCI Express® (PCIe®) products. Interoperability tests enable members to test their products against other members’ products, while Compliance tests allow for product testing against PCI-SIG test modules. In 2022, PCI-SIG introduced PCIe 5.0 Compliance Testing to members. PCIe 5.0 Specification Official Testing includes 32 GT/s maximum link speed.

This webinar presented by Teledyne LeCroy will explore Protocol and Electrical Compliance Testing for PCIe 5.0 systems. Electrical testing examines platform and add-in card transmitter and receiver characteristics, while protocol testing examines a device’s link-level and transaction-level protocol behavior. Attendees will receive an overview of PCIe 5.0 Protocol Compliance Testing, including form factors, lane margining, and link and transaction layer tests. Finally, attendees will learn about PCIe 5.0 Electrical Compliance Test procedures such as transmitter electrical, transmitter link equalization, phase-locked loop (PLL) bandwidth and reference clock jitter.

Participants

Gordon Getty (Teledyne LeCroy)
Anthony Mickens (Teledyne LeCroy)

June 29, 2022

PCIe® 5.0 Protocol and Electrical Compliance Testing Deep Dive

For the past 30 years, PCI-SIG® has delivered IO technologies and specifications that move the technology industry forward and has grown to over 900 members worldwide since its formation in 1992. PCI technology debuted in 1992, supporting a peak throughput of 133 MB/s and a clock speed of 33 MHz, and soon became the standard bus to connect components in a computer system. PCI-X (PCI extended) followed in 1998 providing bandwidth boost required by the industry and this was followed by a significant transition to PCI Express® (PCIe®) architecture in 2003. Since its debut, PCIe technology has evolved over six generations to meet the needs of diverse applications and markets, including Data Center, Servers, Cloud, High Performance Computing (HPC), AI/ML, IoT, Automotive and Military/Aerospace.

In this webinar, PCI-SIG Board Member Dr. Debendra Das Sharma of Intel, will provide a technical deep dive on the industry transitions over the past 30 years, platform transformations, and how PCIe technology has evolved through data rate transitions and protocol enhancements to meet the needs of the compute continuum. Attendees will learn the rationale for the shift from 5 GT/s 8b/10b of the PCIe 2.0 specification to 8 GT/s 128b/130b of the PCIe 3.0 specification. Participants will also learn the protocol enhancements of the PCIe 3.0 specification for accelerators and the low-power substates for applicability to hand-held devices, as well as the technical considerations for the PCIe 4.0 and 5.0 specifications. The webinar will cover the shift to the PCIe 6.0 specification at 64 GT/s and the transition to PAM4 signaling. Finally, Dr. Das Sharma will highlight what’s in store for the future of PCIe technology and how PCI-SIG will continue to meet the needs of the broader compute continuum.

Participants

Debendra Das Sharma (Intel)

January 25, 2023

8:00 am – 9:00 am PDT

Participants

Gordon Getty (Teledyne LeCroy)
Anthony Mickens (Teledyne LeCroy)

PCIe® Technology for Long and Short Reach in Automotive Applications

Dec. 1, 2021

8:00 am – 9:00 am PT

Adoption of PCIe® Technology in IoT Applications Webinar

Automotive vehicle infrastructures are evolving towards a distributed architecture with multiple safety-critical electronic control units (ECUs) close to the sensors that transmit live, data from all points of a car to other ECUs to make real-time decisions. As ECUs become more interconnected, a reliable method is needed for inter-ECU long-reach connections, especially for life-critical applications requiring high resolution, large amounts of data and split-second decisions. PCIe technology over cable is a viable, low latency, long-reach interface for in-vehicle ECU connectivity. For short reach applications within the ECU, retimers, redrivers and crosspoint/multiplexer (MUX) devices can increase link margin and further enhance PCB routing flexibility for system redundancy and fan-out distribution.

This webinar introduces the benefits of PCIe technology-based connectivity in automotive inter-ECU networks. Presenters will discuss the challenges of long-reach connectivity, and the implication of PCIe technology implementation in automotive applications. Attendees will also learn the protocol advantages of PCIe architecture, the realization of native PCIe technology over long-reach cables and signal conditioning considerations.

Participants:

Hope Bovenzi (Astera Labs)
Edo Cohen (Valens)
Anwar Sadat (Texas Instruments)

August 11, 2021

8:00 am – 9:00 am PDT

PCIe® Technology for Automotive Functional Safety

The Internet of Things (IoT) represents a wide range of diverse systems spanning edge/ gateway, data acquisition devices, automotive, modular computers, industrial PC and more. One of the characteristics of the emerging edge and IoT market is the exponential growth in data. Most of that data will be processed, stored, and analyzed at the edge to help deliver better latency, conserve network bandwidth, and improve reliability, security and privacy. As data growth explodes, high bandwidth I/O capabilities along with AI will become necessary to transport and transform this data into actionable information and valuable insights.

In this webinar, attendees will learn about the role the high bandwidth, low latency PCI Express (PCIe) interconnect technology plays as the primary I/O interconnect in the IoT space. We will review how PCIe architecture is used in the following IoT segments: Edge Computing, Test Equipment, Embedded/Industrial PCs and Automotive.

Participants

Debendra Das Sharma (Intel)
Anil Kumar (Intel)

June 16, 2021

8:00 – 9:00 am PST

An Introduction to PCIe® Technology in Automotive Applications

As vehicles continue to become more advanced, functional safety is required as end-to-end measures to maintain vehicle safety in applications including Advanced Driver Assistance Systems (ADAS) and autonomous vehicles. With the expansion of PCI Express® (PCIe®) technology in automotive use cases, functional safety is integrated throughout the system, components and the development lifecycle of both components and system.

In this presentation, attendees will learn how PCIe technology enables safety-critical applications, including Automotive Safety Integrity Level (ASIL) targets for automotive applications such as In-Vehicle Infotainment (IVI), ADAS, and Automated Driving Systems (ADS). The talk also will cover system-level safety architectures and PCIe specification safety features, including where PCIe architecture is used in vehicles, the types of safety-critical data it carries and the importance of RAS functionality. Finally, attendees will learn System on a Chip (SoC) and component-level safety mechanisms to meet ASIL targets and ensure automotive functional safety.

Participants:

Thierry Beaumont, Functional Safety Architect, Intel
Ron DiGuiseppe, Automotive IP Segment Manager, Synopsys
Stephanie Friederich, Systems Engineer, Intel

April 7, 2021

8:00 – 9:00 am PST

Seamless Transition to PCIe^® 5.0 Technology in System Implementations

The adoption of PCI Express® (PCIe®) architecture in the automotive market is expanding in new AI based Advanced Driver Assistance Systems (ADAS) and infotainment automotive applications, as well as autonomous vehicles. PCIe technology provides high bandwidth, low latency links within the processing units for ADAS and infotainment systems. PCIe technology is also quickly becoming the standard interface for modules housing 4G/5G subsystem. Finally, PCI Express architecture offers reliable connectivity and the vast technology ecosystem needed to support automotive applications of the future.

In this presentation, attendees will learn how PCIe technology is enabling the automotive infotainment and connectivity ecosystem and receive an overview of critical safety applications. The presentation will take a deep dive into the various automotive use cases and the role of PCIe technology in shaping the future of automotive system integration.

December 9, 2020 and December 10, 2020

View Recorded English Webinar

View Recorded Mandarin Webinar

Integrity and Data Encryption (IDE) ECN Deep Dive

Compute-intensive workloads, such as Artificial Intelligence and Machine Learning, are being widely adopted in enterprise and cloud data centers, requiring high-performance, purpose-built nodes connected over high speed, low latency interconnects such as PCI Express^® (PCIe^®) architecture. The upgrade from PCIe 4.0 to PCIe 5.0 technology doubles the bandwidth from 16GT/s to 32GT/s but also suffers greater attenuation per unit distance, impacting signal reach and system topology challenges. This technical webinar explores changes between PCIe 4.0 and PCIe 5.0 specifications, including signal integrity and system design challenges, where the right balance must be found between PCB materials, connector types and the use of signal conditioning devices for practical compute topologies.

Through an objective analysis, the goal is to provide the audience with a methodology to optimize signal and link integrity performance, present best practices for system board design to support PCIe 5.0 technology applications, and test for system level interoperation. Finally, to improve link uptime and maximize the potential of PCIe architecture throughput and latency, we explore the relationship between Lane BER and Link stability.

在系统实施中无缝过渡到PCIe® 5.0技术

计算密集型工作负载（例如人工智能和机器学习）受到企业和云数据中心广泛采用，需要通过高速、低延迟的互连架构如PCI Express^®（PCIe^®）连接高性能、专用的节点。从PCIe 4.0升级到PCIe 5.0技术使得带宽从16GT/s倍增至32GT/s，但同时信号的衰减也更大，从而对信号传输距离和系统拓扑挑战造成影响。本次技术网络研讨会探讨了PCIe 4.0和PCIe 5.0规范之间的变化，包括信号完整性和系统设计带来的挑战。在实际应用中，这些变化必须在PCB材料、连接器类型和信号调节器件之间找到适当的平衡。

通过客观分析，最终目标是为与会者提供一种优化信号和链路完整性性能的方法，为支持PCIe 5.0技术应用的系统板设计提供最优方法，并测试系统级互操作性。最后，为了提高链路正常运行时间且最大程度的发挥PCIe架构吞吐量和延迟的潜力，我们也探索了信道误码率（Lane BER）与链路稳定性之间的关系。

在系統實施中無縫轉移至PCIe® 5.0技術

運算密集型工作負載（如人工智慧、機器學習）受到企業和雲端資料中心廣泛採用，需要透過高速、低延遲的互連架構如PCI Express^®（PCIe^®）連接高效能、專用節點。從PCIe 4.0升級至PCIe 5.0技術將頻寬從16GT/s增加一倍至32GT/s，但同時每單位距離的訊號衰減也更大，對訊號傳輸距離和系統拓撲挑戰造成影響。本次線上技術研討會將探討PCIe 4.0和PCIe 5.0規範之間的變化，包括訊號完整性和系統設計帶來的挑戰。在實際運算拓撲中，這些變化必須在PCB材料、連接器類型和訊號調節裝置之間找到適當的平衡。

透過客觀分析，最終目標是為觀眾提供一種優化訊號和鏈路完整性效能的方法，為支援PCIe 5.0技術應用的系統板載設計提供最佳實踐方式，並測試系統級互通性。最後，為了提升鏈路正常運行時間，並最大程度發揮PCIe架構吞吐量和延遲的潛能，我們也將探討通道位元錯誤率（Lane BER）與鏈路穩定性之間的關係。

Participants

Jonathan Bender, Casey Morrison of Astera Labs presented the English version
Liang Liu of Astera Labs presented the Mandarin version

August 25, 2020
9:00 – 10:00AM PT

PCIe^® 6.0 Specification: The Interconnect for I/O Needs of the Future

Developers must focus on a wide number of considerations when securing the wide spectrum of systems, devices and components. Not only must they protect key assets against a litany of attacks, but they must also prioritize securing the entire component lifecycle. Over the past few years, PCI-SIG^® has focused on optimizing security features within the PCI Express^® library of specifications. This webinar will focus on the key aspects of the latest emerging security ECN: Integrity and Data Encryption (IDE).

Attendees learned about the next level details of motivations and use models, including Link vs. Selective, how security is managed, required elements outside of PCIe^® technology including software, system construction and industry infrastructure. The webinar also provided an overview of Device’s responsibilities in maintaining security, such as how keys must be secured, paths around encryption eliminated/blocked and how to handle debug. Finally, the webinar outlined specific areas for feedback such as key size and key programming protocol.

Participants:

David Harriman, PCI-SIG Protocol Work Group Chair, Intel

August 5, 2020
8:00 – 9:15AM CST / 9:00AM – 10:15AM EST

PCI Express® (PCIe®) architecture has provided the I/O connectivity for computing, communication, and storage platforms satisfying the power-efficient and low-latency requirements of cloud, enterprise, PC, embedded, IoT, automotive, and mobile market segments for two decades. However, the demand for additional performance in power constrained devices and data-hungry server, client, embedded, cloud and edge segments keeps increasing. To continue to meet the performance needs of these segments, PCI-SIG® continues its nearly three decade history of successfully delivering performance doubling with the development of the upcoming PCIe 6.0 specification.

Attendees will learn more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It introduces the approach PCIe 6.0 specification is taking to offer new features like PAM4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

In this webinar replay at a new APAC-friendly time, members will be able to participate in a live Q&A with the presenter.

Participants:

Dr. Debendra Das Sharma, PCI-SIG Board member and an Intel Fellow and Director of I/O Technology and Standards Group

June 4, 2020
8:00 – 9:00AM PT

In this webinar, attendees learned more about what is driving the quick transition to PCIe 6.0, including an updated specification release timeline. The webinar will feature a deep dive into the PCIe 6.0 architecture metrics. It introduced the approach PCIe 6.0 specification is taking to offer new features like PAM-4 encoding and FEC, while preserving its low-latency characteristics required for a Load-Store interconnect and full backwards compatibility.

Participants:

Dr. Debendra Das Sharma, PCI-SIG Board member and an Intel Fellow and Director of I/O Technology and Standards Group

Emerging Form Factors: EDSFF Overview
April 8, 2020
8:00 – 9:00AM PT

Enterprise & Data Center SSD Form Factor (EDSFF) is one of the newest form factors to emerge in recent years. Its goal is to develop a stronger data center system-optimized design than traditional SSD form factors like M.2 or U.2. EDSFF has shown that it’s able to meet customer need for storage devices with its high density, capacity and performance.

This webinar will include an overview of the relationship between EDSFF and the PCI Express® (PCIe®) specifications and discuss various use cases for E1.L, E1.S and E3. Finally, they will outline the step-by-step process of how you can build a drive utilizing EDSFF form factors.

Participants:

Tom Friend, President and CEO at Illuminosi
Jonmichael Hands, Sr. Strategic Planner, Product Manager at Intel
Jonathan Hinkle, Executive Director and Distinguished Researcher - Systems Architecture at Lenovo

Retimers to the Rescue: PCI Express® Specifications Reach Their Full Potential
October 9, 2019
8:00 – 9:00AM