As Moore’s Law slows down and approaches its scalability limits due to semiconductor equipment limitations, the industry needs to seek new solutions to boost the performance and efficiency of CPUs. Chiplets are tiny integrated circuits (ICs) with specific functions that can be combined with other chiplets on an interposer in a single package to create a complex system, like a CPU.

This blog explores how PCI Express® (PCIe®) technology addresses challenges in the chiplet market, the benefits of implementing PCIe architecture in chiplet designs and the future of PCIe and chiplet technologies.

Challenges in the Chiplet Market

Challenges in the chiplet market include the seamless integration of chips and dies from various vendors and reducing the power brought in by using many chips in a single package, thermal and substrate. Chiplets need more electrical flexibility in channel routing and if not satisfied, extra power and latency can dissipate. Performance and throughput demands on compute and networking devices are rising faster than their thermal envelopes. As the die size increases to meet the growing performance demands, designs run against the die reticle limit. To address these challenges, chiplet technology can be found in retimers and switches utilizing PCIe technology to address on-package connectivity of identical dies, System on a Chip (SoC) construction obstacles and more.

PCIe Technology Increases Reliability for Chiplets

PCIe technology has wide adoption across the industry allowing for easier “plug-and-play” capabilities and continues to double bandwidth every three years, making it a reliable interconnect for chiplets. PCIe architecture is implemented at the motherboard level, which allows data to be transferred over a longer distance and preserves signal and transmission quality.

Chiplets are currently based on the PCIe 5.0 standard at 32 GT/s data rate and are working towards leveraging the PCIe 7.0 standard at 128 GT/s data rate, which will affect new and emerging markets.

The Future of PCIe and Chiplets – AI, HPC and Beyond

There are many opportunities for chiplets to evolve with the support of PCIe architecture. As the basis of a chiplet interconnect, first adopters of PCIe technology will be data center applications where high-density SoC solutions are used for CPU core counts. PCIe technology also decreases latency and increases scalability, which offers a significant advantage for streaming data in Deep Learning, HPC, and In-Memory Database applications. Other market segments that will benefit from PCIe technology and chiplets include automotive, IoT, medical devices and smartphones.

Join PCI-SIG to Support PCIe Technology and Chiplets

If you would like to support the future development of PCIe technology and chiplets, we encourage you to join PCI-SIG. Follow PCI-SIG on LinkedIn and Twitter/X for the latest information about the PCIe specifications, events and more.