Authentication to Encryption: Reinforcing PCIe Security
This presentation highlights the critical need for a robust security software stack and explores the seamless integration of advanced security layers within the PCIe architecture. Introduction of Security Stack 1. The PCIe Security Stack comprises three layers: SPDM for authentication and key exchange, TDISP for transport integrity, and IDE for data encryption and how integration across these layers is achieved through Data Object Exchange (DOE) 2. Verification scenarios will be discussed which would distinguish the explicit needs for all the layers. Requirement of Security Stack 1. SPDM Layer: Ensures device authenticity and data integrity using cryptographic algorithms. 2. IDE Layer: Secures PCIe traffic with encryption, protecting data transfer over untrusted links. 3. TDISP Layer: Prevents unauthorized access to device memory and configuration space for enhanced security.

PCIe 6.x PHY Logical
PCI Express (PCIe) specification has been doubling the data rate every generation in a backwards compatible manner every two to three years. PCIe 6.0 specification has adopted PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach as prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. A new Flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency link level retry mechanism in PCIe 6.0 specification meets the stringent low-latency, high bandwidth and high reliability goals. Shared credit pooling across multiple virtual channels is included to reduce the area and power overhead while providing the necessary quality of service guarantees. We also present a new low-power state (L0p) that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

Mohiuddin Mazumder
Mohiuddin Mazumder is a Senior Principal Engineer in Data Center and AI division of Intel. He leads the Electrical pathfinding and Standards development work for high-speed differential interconnect technologies. He co-chairs the PCI-SIG Electrical WG and also leads the PCIe 5.0/6.0 Internal and External Cables specification for 32 and 64 GT/.

Manisha Nilange
Manisha Nilange is a Principal Engineer at Intel Corp. She has been with Intel Corp for 18 years. She leads multiple form-factor specification development, transmitter and receiver compliance test methodology and compliance tool development. Manisha chairs the PCI Express Card Electromechanical (CEM), PCI Express Mini (M.2) and PCI Express SFF Connector (U.2) workgroups in PCI-SIG and co-chairs the Serial Enabling workgroup. Manisha holds MS in Electrical Engineering from the University of Texas at Arlington.

PCIe Compliance Updates
The PCI-SIG has introduced the 5.0 Integrators List program with a new maximum data rate of 32 GT/s enabling a bi-direction link bandwidth up to 128 GB/s for a x16 link. The PCI Express Architecture PHY Test Specification Rev 5.0 has updated the 16 GT/s tests to support the faster rate and introduced new testing requirements including uncorrelated jitter and pulse width jitter for all 5.0 devices. Discussion of measurement methodologies for Tx Signal Quality and Link Equalization testing will provide insight into the latest measurement methodologies.

 
Richard Solomon
Richard Solomon is Technical Marketing Manager for Synopsys' PCIe Controller IP.  He’s been involved in PCI chip development since the original PCI spec, co-chairs the PCI-SIG compliance workgroup, and has served on the PCI-SIG Board of Directors for some 20 years. Richard holds a BSEE from Rice University and 27 US Patents, many PCI-related.

Seiji Suzuki
Seiji Suzuki is a global alliance representative for the ExpEther technology. He has been working as an engineer for more than 30 years in NEC Corporation in fields of computers, communication, software and hardware. He also recently has been working with public cloud system and application vendors.

Large Scale Disaggregated Computing with ExpEther Technology

Optimizing PCIe resource allocation is a highly important issue for expanding AI infrastructure. ExpEther technology can help resolve this issue by realizing large scale disaggregated computing. ExpEther is an IP core which enables transferring PCIe bus data directly over Ethernet fabric. Devices implementing ExpEther combined with Ethernet cables and switches create a virtual PCIe switch over Ethernet networks, enabling extension of PCIe bus over 1km. ExpEther has succeeded in dynamically configurating systems which connect PCIe devices mounted in resource pools 1km away. ExpEther may also be applicable in other use cases like embedded industry solutions and automotive E/E architecture.